ubuntusafa.com: US-China AI Competition Daily Briefing

US-China AI Competition Daily Briefing-

1. The Major Story: DeepSeek Commits Next Frontier Pre-Training to Huawei Ascend 950DT

In a watershed moment reported by The Information, Hangzhou-based AI lab DeepSeek confirmed plans to shift its core frontier model pre-training entirely to domestic silicon, utilizing Huawei’s Ascend 950DT accelerators by the end of 2026:

Breaking the Pre-Training Barrier: While Chinese labs previously relied on Nvidia hardware for initial model pre-training and utilized Huawei silicon primarily for inference, this shift marks the first time a flagship Chinese frontier model will execute pre-training on a domestic silicon stack.
160,000-Unit Inner Mongolia Deployment: DeepSeek is scaling its gigawatt-scale data center facility in Ulanqab, Inner Mongolia, aiming to house at least 160,000 Ascend 950DT units.
Driven by "TileLang" Integration: The transition follows DeepSeek and Huawei's joint open-source release of TileLang—a custom domain-specific language and compiler stack (FlashMLA-Ascend, DeepEP, DeepGEMM) designed to extract native performance from Ascend hardware without relying on Nvidia’s CUDA ecosystem.

2. Regulatory & Trade Focus: US Targets "Model Distillation"

As Beijing formalizes its draft export control catalogue over 23 AI technologies, trade policy analysts and media reports from Chosun and Bloomberg highlight an escalating regulatory shift in Washington targeting Chinese algorithmic distillation:

Focusing on Algorithmic IP Leakage: U.S. Commerce Department and trade advisors are intensifying scrutiny on synthetic data extraction ("model distillation"), where domestic Chinese labs utilize automated queries against Western closed APIs to train open-weights models at a fraction of the cost.
Model Origin Scrutiny: Industry analysts warn that the US-China AI rivalry is evolving beyond physical chip embargoes into a "model control" and "country-of-origin" paradigm. Western enterprise adoption of AI models may increasingly be subject to regulatory compliance checks based on where the model weights were compiled and trained.
Separation from Safety Talks: U.S. officials re-emphasized that technical dialogue under the U.S.-China Superintelligence (SI) Dialogue track will focus on containment protocols for autonomous model incidents, while model distillation enforcement and semiconductor sanctions will remain strictly isolated on a separate trade track.

3. Supply Chain & Allied Enforcement: Taiwan Criminalizes Chip Transshipment

Legal and enforcement follow-through from Taiwan’s Ministry of Economic Affairs (MOEA) underscores tightening physical supply chain boundaries:

Criminalizing Hardware Smuggling: Under updated amendments to Taiwan's Foreign Trade Act, unauthorized exports or transshipments of advanced AI accelerators (meeting or exceeding U.S. BIS performance thresholds) to mainland China now carry direct criminal prosecution and prison terms.
Blanket Control Framework: Moving past targeted entity blacklists, the new rules apply across the board to all mainland Chinese buyers and third-party intermediaries, closing loopholes previously exploited by gray-market smuggling networks in Southeast Asia.
$4 Billion Texas Supplier Park Expansion: Concurrently, Taiwanese trade officials are mobilizing up to $4 billion to build out supplier industrial parks in Texas, helping tier-2/tier-3 substrate, liquid-cooling, and PCB vendors co-locate alongside TSMC and American AI server integrators.

4. Hardware & Supercluster Operations: 100,000-Chip Sovereign Infrastructure

Financial and technical updates following the debut of China's first domestically produced 100,000-chip AI supercluster demonstrate system-level compensation strategies:

Overcoming EUV Lithography Limits: Rather than relying on single-die node shrink, Chinese hyperscalers and national compute hubs (such as the National Supercomputing Internet nodes in Zhengzhou and Ulanqab) are combining non-GPU accelerators with Near-Packaged Optics (NPO) and non-blocking RDMA fabrics (scaleFabric).
System Efficiency: The 100,000-node logical supercomputer achieves over 20 EFLOPS of mixed-precision compute while maintaining direct-to-chip liquid cooling (PUE < 1.10) to power multi-trillion parameter model training within national boundaries.

Strategic Takeaway

The US-China tech divide has reached a structural inflection point. With DeepSeek moving frontier pre-training to Huawei silicon and Washington targeting model distillation, the competition has expanded from physical hardware bans into a symmetrical software, model-origin, and system-level scaling war.

DeepSeek’s transition toward utilizing Huawei’s Ascend 950DT silicon for frontier pre-training—complemented by co-design software optimizations in TileLang and physical deployment at a 1-Gigawatt site in Ulanqab, Inner Mongolia—marks a pivotal technical pivot in China’s AI ecosystem.

Previously, Chinese labs bifurcated their workflows: using imported Nvidia hardware for capital-intensive pre-training runs and deploying domestic silicon strictly for downstream inference. DeepSeek's shift attempts to unify the full AGI pipeline on a sovereign stack.

1. The Pre-Training Pivot & Hardware Co-Design

Pre-training requires continuous mathematical throughput across tens of thousands of chips for months at a time, making it hypersensitive to inter-chip communication latency and software compile crashes.

Workflow Transition: Legacy vs. Sovereign Stack LEGACY DEEPSEEK WORKFLOW (Pre-H2 2026) SOVEREIGN ASCEND WORKFLOW (Q4 2026+) ┌──────────────────────────────────────────┐ ┌──────────────────────────────────────────┐ │ Pre-Training: Nvidia Clusters (CUDA/H800)│ ──►│ Pre-Training: Huawei Ascend 950DT │ │ Inference: Mixed Ascend / Workstation Pods│ │ Inference: Ascend 950DT Clusters │ └──────────────────────────────────────────┘ └──────────────────────────────────────────┘

The Silicon Co-Design Feedback Loop: Reports indicate DeepSeek engineers worked closely with Huawei’s HiSilicon teams to shape the microarchitecture of the Ascend 950DT. This feedback loop optimized hardware execution for sparse Mixture-of-Experts (MoE) architectures, prioritizing low-precision FP4/FP8 matrix engines and high-density all-to-all token dispatch buses over dense FP32/FP16 compute cores.
Overcoming Historical Training Instability: Earlier attempts to pre-train foundation models on domestic silicon failed due to collective communication timeouts and gradient synchronization drops across multi-node clusters. Co-design efforts specifically target Huawei's collective-communication libraries and the Lingqu UnifiedBus interconnect to ensure sub-microsecond latency during gradient synchronization.

2. Software Architecture: TileLang Optimization Layer

The software backbone enabling this shift is TileLang—the open-source domain-specific programming language co-developed by DeepSeek and Huawei. TileLang functions as a high-level abstraction layer that compiles custom AI operators directly to Ascend silicon, bypassing Nvidia's CUDA ecosystem.

TileLang Native Compilation Architecture DEEPSEEK MODEL OPERATORS TILELANG ABSTRACTION LAYER HUAWEI ASCEND HARDWARE ┌────────────────────────────┐ ┌────────────────────────────┐ ┌────────────────────────────┐ │ • FlashMLA (Sparse Attn) │ │ TileKernels / Python │ │ Ascend 950DT Silicon │ │ • DeepEP (MoE Dispatch) │ ──►│ Unified IR Compiler │ ──►│ Matrix Engines │ │ • DeepGEMM (FP8/BF16 Math) │ │ (Generates NPU Primitives) │ │ CANN 9.2+ Toolkit │ └────────────────────────────┘ └────────────────────────────┘ └────────────────────────────┘

Native Specialized Libraries: On September 30, DeepSeek open-sourced specialized Ascend 950 implementations of its core runtime modules:
- DeepGEMM-Ascend: Custom General Matrix Multiply kernels achieving up to 99.8% of theoretical peak performance on Ascend matrix multiplication engines, with built-in scaling factors for FP8 and BF16 execution.
- DeepEP-Ascend: Designed specifically for Mixture-of-Experts (MoE) routing, handling token dispatch and aggregation across 128-way parallelism with dispatch bandwidths reaching 313–320 GB/s.
- FlashMLA-Ascend: Optimized sparse attention kernels designed to accelerate long-context processing without causing memory overflow.
Unified Hardware Abstraction: TileLang exposes identical Python interfaces regardless of whether code runs on Nvidia CUDA, AMD ROCm, or Huawei Ascend. This reduces hardware lock-in and enables developers to port complex MoE model architectures without rewriting low-level kernel code.

3. Inner Mongolia Megacluster Scaling (Ulanqab Site)

To host these compute engines, DeepSeek is anchoring its physical footprint at a gigawatt-scale data center facility in Ulanqab, Inner Mongolia:

Ulanqab Megacluster Operational Profile POWER CAPACITY HARDWARE ALLOCATION SYSTEM PUE TARGET ┌──────────────────────────────┐ ┌──────────────────────────────┐ ┌──────────────────────────────┐ │ • 1-Gigawatt (1GW) Total │ │ • 160,000 Ascend 950DT Units │ │ • PUE < 1.10 │ │ Power Grid Horizon │ │ • Multi-Tenant MoE Nodes │ │ • Direct-to-Chip Liquid │ │ • Direct Wind/Solar Tie-in │ │ • Estimated Cost: ~$2.56B │ │ Warm-Water Cooling │ └──────────────────────────────┘ └──────────────────────────────┘ └──────────────────────────────┘

Target Deployment Scale: The plan calls for installing at least 160,000 Huawei Ascend 950DT units, establishing one of the largest single concentrations of sovereign AI compute in mainland China.
1-Gigawatt Power Grid Tie-In: Positioned within the "Eastern Data, Western Computing" (Dongshu Xisuan) national computing hub, the site leverages Inner Mongolia's abundant wind and solar resources, lowering electricity operational costs by 30% to 50% compared to coastal data centers.
Thermal Management & PUE: The facility implements direct-to-chip warm-water liquid cooling to maintain a Power Usage Effectiveness (PUE) below 1.10, allowing high-density 128-chip Ascend supernodes to run continuously at peak TDP.

Key Bottlenecks & Operational Constraints

Despite the technical alignment between DeepSeek and Huawei, the execution timeline faces two primary hardware constraints:

High-Bandwidth Memory (HBM) Shortages: The Ascend 950DT relies heavily on domestic high-bandwidth memory (HiBL/HBM) stacks. Due to domestic packaging capacity limits, total 950DT production volume in late 2026 remains constrained to the low hundreds of thousands of units, meaning full 160,000-unit deployment will stretch across 2027.
Collective Communication at Scale: While single-chip matrix math matches top-tier targets, scaling TileLang-compiled models across 100,000+ nodes under high-concurrency MoE workloads will serve as the ultimate real-world test for Huawei's CANN 9.2+ software stack and optical switch fabrics.

Technical Architecture of DeepSeek & Huawei's TileLang

TileLang is an open-source, domain-specific programming language (DSL) built on top of Apache TVM compiler infrastructure and custom MLIR backends. Co-developed by researchers at Peking University, DeepSeek, and Huawei, it introduces a high-level tile-centric abstraction model designed to streamline kernel engineering for complex Mixture-of-Experts (MoE) architectures and long-context transformer execution.

Rather than competing at the low-level C/C++ interface, TileLang abstracts raw hardware memory hierarchies, warp/thread coordination, and hardware-level pipelines into declarative Pythonic primitives while preserving fine-grained control over layout transformation and execution scheduling.

TileLang System Architecture HIGH-LEVEL PYTHON FRONTEND TILELANG COMPILER / TVM / MLIR HARDWARE EXECUTION TARGETS ┌───────────────────────────────┐ ┌─────────────────────────────────┐ ┌──────────────────────────────────┐ │ @tilelang.jit Decorator │ │ • Layout & Schedule Inference │ │ • Huawei Ascend 950 (CANN/PTO) │ │ Declarative Tile Allocations │ ──► │ • Automatic Pipeline & Sync IR │ ──► │ • Nvidia CUDA (PTX / Cutlass) │ │ T.alloc_L1 / T.alloc_UB / L0 │ │ • Code Generators (Ascend/PTX) │ │ • AMD ROCm (HIP / CDNA) │ └───────────────────────────────┘ └─────────────────────────────────┘ └──────────────────────────────────┘

Core Architectural Layers

1. The Tile Abstraction Model (Tiling-First Design)

Traditional GPU languages require developers to explicitly write thread-level loops and map global memory indices to thread IDs. TileLang replaces thread-level programming with n-dimensional tiles:

Data-Movement & Tiling Primitives: Data allocations are specified in terms of execution tiles (e.g., block_M x block_N). The compiler handles lower-level loop unrolling, vector register allocation, and multi-dimensional memory indexing automatically.
Layout-Aware Memory Mapping: Allows explicit allocation across physical memory hierarchies—mapping directly to Nvidia's Global, Shared Memory, and Tensor Memory (TMEM), or Huawei Ascend's Global Memory (GM), L1 Buffer, Unified Buffer (UB), and L0 Matrix Units (L0A, L0B, L0C).

2. Scope Separation: Cube Core vs. Vector Core

Huawei Ascend NPUs feature distinct computational engines: Cube Cores (handling matrix multiplication) and Vector Cores (handling element-wise ops, activations, and softmax).

Automatic Scope Partitioning: TileLang abstracts this dual-engine layout via execution scopes (T.Scope("C") for Cube, T.Scope("V") for Vector).
Compiler-Driven Synchronization: Exposes pipeline flags (T.set_flag / T.wait_flag) to automate multi-stage memory transfers between the main data bus (MTE1/MTE2) and processing cores, preventing data races during asynchronous matrix multiplication.

3. High-Performance DeepSeek Core Modules

To demonstrate production performance, DeepSeek open-sourced six core AI libraries compiled directly in TileLang for Huawei Ascend hardware:

DeepGEMM-Ascend: Custom General Matrix Multiply kernels reaching up to 99.8% of theoretical peak performance on Ascend 950DT matrix engines with native FP8/BF16 scaling.
DeepEP-Ascend: An optimized communication engine built specifically for Mixture-of-Experts (MoE) routing, achieving dispatch bandwidths of 313–320 GB/s during 128-way tensor-parallel dispatch.
FlashMLA-Ascend: Native Multi-Head Latent Attention kernels engineered for long-context processing without causing VRAM overflow.

How TileLang Bypasses Nvidia CUDA

Nvidia’s primary competitive moat is not just hardware performance, but the software layer: a multi-million-developer ecosystem tied to CUDA, CuDNN, TensorRT, and Cutlass. TileLang decouples AI software development from Nvidia CUDA across three primary vectors:

CUDA vs. TileLang Execution Path TRADITIONAL CUDA WORKFLOW TILELANG DECOUPLED WORKFLOW ┌──────────────────────────────┐ ┌──────────────────────────────┐ │ Model Framework (PyTorch) │ │ Model Framework (PyTorch) │ └──────────────┬───────────────┘ └──────────────┬───────────────┘ │ │ ▼ ▼ ┌──────────────────────────────┐ ┌──────────────────────────────┐ │ Proprietary CUDA C++ Kernels │ │ TileLang Python Frontend │ └──────────────┬───────────────┘ └──────────────┬───────────────┘ │ │ ▼ ▼ ┌──────────────────────────────┐ ┌──────────────────────────────┐ │ PTX / Nvidia Driver Runtime │ │ Unified Compiler Engine │ └──────────────┬───────────────┘ │ (TVM / MLIR AST Translation) │ │ └──────────────┬───────────────┘ ▼ │ ┌──────────────────────────────┐ ┌──────────────┴───────────────┐ │ Nvidia Silicon ONLY │ │ │ └──────────────────────────────┘ ▼ ▼ ┌──────────────────────────────┐┌──────────────────────────────┐ │ Huawei Ascend (CANN / PTO) ││ Nvidia / AMD / Apple / Others│ └──────────────────────────────┘└──────────────────────────────┘

1. Hardware Neutrality via Abstract Intermediate Representation (IR)

In traditional setups, porting a model from CUDA to alternative silicon requires completely rewriting custom C++ kernels into proprietary vendor DSLs (such as Huawei Ascend C, AMD HIP, or Intel OneAPI).

TileLang sits above vendor-specific runtime drivers. When a developer writes a kernel in TileLang, the code is parsed into a hardware-agnostic Intermediate Representation (IR). The compiler's code-generation backends translate this unified IR directly into PTO/AscendNPU IR for Huawei, PTX for Nvidia, or HIP/CDNA for AMD. Developers can target different hardware platforms by changing a single parameter (target="ascend" or target="cuda").

2. Abstracting Away Hardware-Specific Matrix Extensions

Modern hardware speedups rely on specialized matrix engines (Nvidia Tensor Cores/TMA/WGMMA vs. Huawei Ascend Cube Cores). Writing raw CUDA requires manually managing hardware-specific assembly instructions.

TileLang handles matrix acceleration through high-level mathematical abstractions (such as T.tile.matmul or T.copy), leaving tensor alignment, layout swizzling, and async pipeline synchronization to the compiler backend. This allows custom Mixture-of-Experts (MoE) models to achieve near-peak hardware utilization on Huawei silicon without engineers needing specialized knowledge of Ascend hardware assembly.

3. Native Integration with Open-Source Frameworks (PyTorch & MindSpore)

Instead of forcing developers into vendor-locked deployment pipelines (like Nvidia TensorRT), TileLang compiles custom kernels directly into PyTorch C++ extensions via @tilelang.jit. Huawei’s open-source CANN (Compute Architecture for Neural Networks) platform integrates these compiled operators natively as PyTorch device backends (torch_npu), allowing over 90 major open-source model repositories to run natively on Ascend clusters without manual code translation.

Strategic Significance

By open-sourcing TileLang and demonstrating its viability across 160,000 Huawei Ascend units in Inner Mongolia, DeepSeek and Huawei have built a functional alternative to Nvidia's software ecosystem. TileLang gives domestic Chinese AI labs and global developers a high-productivity, open-source programming layer that breaks Nvidia's CUDA lock-in, enabling multi-trillion parameter model training and inference on sovereign hardware stacks.