US-China AI Competition Daily Briefing-
1. The Major Story: DeepSeek & Huawei Deepen "Embedded" Co-Design
Follow-up reporting on DeepSeek’s transition to pre-training its next-generation foundation models on Huawei Ascend 950DT accelerators reveals an unprecedented level of software-hardware integration:
- Engineers On-Site at DeepSeek: Huawei chip design engineers have taken up long-term residence inside DeepSeek’s Hangzhou offices.
Rather than acting purely as a vendor, Huawei is directly folding DeepSeek’s real-world model bottlenecks (specifically data transfer patterns and low-precision FP8/FP4 math) into the physical microarchitecture of the upcoming Ascend 960DT, targeted for Q1 2027. - Testing 10,000-Card Cluster Stability: DeepSeek is preparing to kick off a initial pre-training run on a 10,000-card Ascend 950DT cluster by the end of 2026. This run will serve as a trial ahead of scaling up to its planned 160,000-unit deployment at the 1-Gigawatt Ulanqab site in Inner Mongolia.
- The Software Bridge: DeepSeek is utilizing TileLang to write hardware-neutral operators (like DeepGEMM and DeepEP), allowing its engineers to extract up to 99.8% of theoretical peak matrix performance from Ascend engines while bypassing Nvidia CUDA dependencies.
2. Enforcement & Security: Federal DeepSeek Restrictions and Taiwan's Legal Pivot
Geopolitical pressure around software usage and supply chain leaks continues to escalate:
- US Federal Ban on DeepSeek Tools: Following an emergency notice from the U.S. Department of Homeland Security (DHS), federal agencies and government vendors have been instructed to remove all DeepSeek products and developer extensions.
DHS cited data privacy and security vectors, noting that processing interactions on servers subject to Chinese jurisdiction creates systemic data transfer risks. Beijing’s Ministry of Foreign Affairs publicly opposed the measure. - Taiwan Finalizes Foreign Trade Act Penalties: Further details on Taiwan’s amendment to its Foreign Trade Act confirm that Taiwanese executives and server assemblers (e.g., Gigabyte, Asustek, Supermicro operations in Taiwan) now face domestic criminal prosecution and imprisonment—not just administrative civil fines—for unauthorized exports of advanced servers or AI chips exceeding BIS performance thresholds.
- Eliminating the "Safe Harbor": Taiwan’s Minister of Economic Affairs Kung Ming-hsin confirmed that this measure fulfills commitments made under the 2026 U.S.-Taiwan Agreement on Reciprocal Trade. Previously, local prosecutors could only pursue document forgery; now, smugglers face dual-jurisdiction criminal exposure under both U.S. and Taiwanese law.
3. Policy & Trade: Beijing's Global "Soft Stack" Strategy
Fresh analytical reports from European policy institutes (including Bruegel) highlight the underlying mechanics of Beijing’s new 40-Technology Export Catalog (Announcement No. 48):
- Models First, Chips Later: Analysts note that China is executing a deliberate two-stage outbound strategy: exporting open-weights models and governance standards globally now to build soft-stack adoption, while keeping hardware self-reliance concentrated domestically.
- Model Licensing vs. API Freedom: Under China's draft catalog, physical model weights (
$\ge 2\text{ Trillion}$ parameters or $\ge 10^{26}\text{ FLOPs}$) require state export licenses, but API and SaaS cloud endpoints remain explicitly exempt. This allows Chinese labs to monetize services globally while keeping proprietary weights anchored to sovereign compute infrastructure.
Strategic Takeaway
The confrontation has bifurcated into two distinct domains: physical hardware defense (where Taiwan is deploying criminal statutes to close supply chain gaps) and a software stack war (where DeepSeek and Huawei are co-designing native Ascend hardware via TileLang to prove that Chinese frontier models can pre-train without Nvidia silicon).
DeepSeek’s transition toward pre-training its flagship foundation models on Huawei’s Ascend 950DT silicon—underpinned by deep software co-design via TileLang and physical deployment across a 1-Gigawatt megacluster in Ulanqab, Inner Mongolia—represents a major structural milestone in China’s AGI infrastructure.
Historically, domestic Chinese AI labs operated under a bifurcated workflow: utilizing imported or gray-market Nvidia hardware (like H800s) for compute-heavy pre-training runs and restricting domestic silicon to downstream inference. DeepSeek's shift attempts to unify the full pre-training and inference lifecycle on a sovereign, CUDA-independent stack.
1. The Pre-Training Pivot & Co-Design Architecture
Pre-training requires unbroken, deterministic mathematical throughput across tens of thousands of compute nodes over multi-month runs. This makes the process hypersensitive to inter-chip communication latency, collective synchronization drops, and compilation crashes.
Workflow Transition: Legacy vs. Sovereign Stack
LEGACY DEEPSEEK WORKFLOW (Pre-H2 2026) SOVEREIGN ASCEND WORKFLOW (Q4 2026+)
┌──────────────────────────────────────────┐ ┌──────────────────────────────────────────┐
│ Pre-Training: Nvidia Clusters (CUDA/H800)│ ──►│ Pre-Training: Huawei Ascend 950DT │
│ Inference: Mixed Ascend / Workstation Pods│ │ Inference: Ascend 950DT Clusters │
└──────────────────────────────────────────┘ └──────────────────────────────────────────┘
- Embedded Hardware Co-Design: Huawei engineers have taken up long-term residence at DeepSeek’s Hangzhou headquarters. Rather than operating as a passive vendor, Huawei is directly incorporating real-world large language model workload bottlenecks—specifically low-precision FP8/FP4 tensor operations and all-to-all token dispatch patterns—into the physical microarchitecture of the upcoming Ascend 960DT (targeted for Q1 2027).
- Stepwise Cluster Validation: To validate cluster stability before full deployment, DeepSeek is preparing a 10,000-card Ascend 950DT trial run. This phase directly stress-tests Huawei's CANN 9.20 toolkit and Lingqu UnifiedBus collective communication libraries under prolonged gradient synchronization workloads.
- Optimization for Sparse Architectures: Co-design efforts specifically target sparse Mixture-of-Experts (MoE) models. By tuning hardware matrix engines and high-density all-to-all token dispatch buses, the architecture minimizes memory access overhead during dynamic token routing.
2. Software Architecture: TileLang Optimization Layer
The software backbone enabling this shift is TileLang—an open-source domain-specific programming language co-developed by Peking University researchers, DeepSeek, and Huawei.
TileLang Native Compilation Architecture
DEEPSEEK MODEL OPERATORS TILELANG ABSTRACTION LAYER HUAWEI ASCEND HARDWARE
┌────────────────────────────┐ ┌────────────────────────────┐ ┌────────────────────────────┐
│ • FlashMLA (Sparse Attn) │ │ TileKernels / Python │ │ Ascend 950DT Silicon │
│ • DeepEP (MoE Dispatch) │ ──►│ Unified IR Compiler │ ──►│ Matrix Engines │
│ • DeepGEMM (FP8/BF16 Math) │ │ (Generates NPU Primitives) │ │ CANN 9.20 Toolkit │
└────────────────────────────┘ └────────────────────────────┘ └────────────────────────────┘
- Native Production Toolkit: Under the MIT license, DeepSeek and Huawei open-sourced native Ascend 950 implementations of custom runtime modules used in flagship foundation models:
- DeepGEMM-Ascend: Custom General Matrix Multiply kernels reaching up to 99.8% of theoretical peak performance (431 BF16 TFLOPS out of a 432 TFLOPS hardware ceiling) on Ascend matrix multiplication engines.
- DeepEP-Ascend: An optimized communication engine built specifically for Mixture-of-Experts (MoE) routing, handling token dispatch and aggregation across 128-way parallelism with dispatch bandwidths reaching 313–320 GB/s.
- FlashMLA-Ascend: Optimized sparse attention kernels designed to accelerate long-context processing (up to million-token windows) without causing memory bandwidth bottlenecks.
- Unified Hardware Abstraction: TileLang exposes identical Pythonic interfaces regardless of whether code target Nvidia CUDA, AMD ROCm, Apple Metal, or Huawei Ascend. This eliminates code refactoring when moving complex MoE models between mixed-vendor clusters.
3. Inner Mongolia Megacluster Scaling (Ulanqab Site)
To host these compute engines, DeepSeek is anchoring its physical footprint at a gigawatt-scale data center facility in Ulanqab, Inner Mongolia:
Ulanqab Megacluster Operational Profile
POWER CAPACITY HARDWARE ALLOCATION SYSTEM PUE TARGET
┌──────────────────────────────┐ ┌──────────────────────────────┐ ┌──────────────────────────────┐
│ • 1-Gigawatt (1GW) Total │ │ • 160,000 Ascend 950DT Units │ │ • PUE < 1.10 │
│ Power Grid Horizon │ │ • Multi-Tenant MoE Nodes │ │ • Direct-to-Chip Liquid │
│ • Direct Wind/Solar Tie-in │ │ • Co-Optimized Supernodes │ │ Warm-Water Cooling │
└──────────────────────────────┘ └──────────────────────────────┘ └──────────────────────────────┘
- Target Deployment Scale: The plan calls for installing at least 160,000 Huawei Ascend 950DT units, establishing one of the largest single concentrations of sovereign AI compute in mainland China.
- 1-Gigawatt Power Grid Tie-In: Positioned within the "Eastern Data, Western Computing" (Dongshu Xisuan) national computing hub, the site leverages Inner Mongolia's abundant wind and solar resources, lowering electricity operational costs compared to coastal data centers.
- Thermal & Supernode Architecture: The facility utilizes direct-to-chip warm-water liquid cooling to maintain a Power Usage Effectiveness (PUE) below 1.10. The physical deployment is built around co-optimized 128-chip Ascend 950 supernodes, enabling ultra-high-density compute topologies.
Key Bottlenecks & Operational Constraints
Despite the co-design alignment between DeepSeek and Huawei, full execution faces two primary supply chain and software constraints:
- High-Bandwidth Memory (HBM) Shortages: The Ascend 950DT relies heavily on domestic high-bandwidth memory. Due to domestic packaging capacity limits, total 950DT production volume in late 2026 remains constrained to the low hundreds of thousands of units globally, meaning full 160,000-unit cluster fulfillment will stretch across 2027 and 2028.
- Cluster Reliability & Interconnect Scale: While single-chip and 128-chip supernode benchmarks achieve high efficiency, holding a multi-thousand-chip Ascend cluster stable for weeks without driver crashes or communication timeouts remains the primary real-world test for Huawei's CANN 9.20 software stack.
A technical comparison between Huawei’s Ascend 950 series (950PR / 950DT) and Nvidia’s China-compliant H20 highlights two distinct silicon engineering philosophies: Huawei sacrifices absolute power efficiency to maximize raw compute and memory capacity under domestic foundry constraints, whereas Nvidia relies on capped compute paired with ultra-fast HBM3 memory bandwidth.
Specification Matrix
| Feature / Metric | Nvidia H20 (SXM/PCIe) | Huawei Ascend 950PR (Atlas 350) | Huawei Ascend 950DT (OAM Module) |
| Primary Workload Target | Capped China Compliance / LLM Inference | Prefill Stage & Recommendation (Compute-Bound) | Decode Stage & Frontier Pre-Training (Bandwidth-Bound) |
| Architecture | Hopper (Capped GH100) | Da Vinci v3.0 | Da Vinci v3.0 |
| Process Node | TSMC 4N (5nm class) | SMIC 7nm (DUV Multi-Patterning) | SMIC 7nm (DUV Multi-Patterning) |
| Dense FP8 Compute | ~296 TFLOPS | 1,000 TFLOPS (1.0 PFLOPS) | 1,034 TFLOPS (1.03 PFLOPS) |
| Dense FP4 / MXFP4 | Not Supported | 2,000 TFLOPS (2.0 PFLOPS) | 2,007 TFLOPS (2.0 PFLOPS) |
| Dense BF16 Compute | ~148 TFLOPS | 500 TFLOPS | 547 TFLOPS |
| Memory Capacity | 96 GB HBM3 | 128 GB HiBL 1.0 (112GB on Atlas 350) | 144 GB HiZQ 2.0 |
| Memory Bandwidth | 4.0 TB/s | 1.6 TB/s (1.4 TB/s on Atlas 350) | 4.0 TB/s |
| Interconnect Bandwidth | 900 GB/s (NVLink 4 capped) | 2.0 TB/s (Lingqu / UnifiedBus 2.0) | 2.0 TB/s (Lingqu / UnifiedBus 2.0) |
| Thermal Design Power (TDP) | ~400 W | 600W (Card) / 900W (Full Module) | 900 W – 1,000 W |
| Software Backend | CUDA / TensorRT-LLM / vLLM | CANN 9.x / torch_npu / TileLang | CANN 9.x / torch_npu / TileLang |
Architectural & Memory Bandwidth Breakdown
1. Compute Density vs. US Export Restrictions
Nvidia’s H20 was designed specifically to comply with U.S. Commerce Department (BIS) Performance Density limits. To stay below federal caps, Nvidia throttled raw FP8 math down to ~296 TFLOPS.
Unconstrained by U.S. export caps, Huawei’s Ascend 950PR and 950DT deliver ~1,000 TFLOPS of FP8 and ~2,000 TFLOPS of FP4 / MXFP4 compute—representing a ~3.4x compute advantage over the H20 at FP8.
FP8 Dense Compute Comparison (TFLOPS)
Nvidia H20 [ 296 TFLOPS ]
Ascend 950PR [==================== 1,000 TFLOPS ====================]
Ascend 950DT [==================== 1,034 TFLOPS ====================]
2. The Workload Split: Prefill (950PR) vs. Decode (950DT)
Huawei bifurcated the 950 architecture to manage domestic HBM yield limits:
- Ascend 950PR (Prefill & Recommendation): Paired with proprietary, lower-cost HiBL 1.0 memory (128 GB capacity at 1.6 TB/s).
Because the prefill stage of LLMs and recommendation embedding tables are compute-bound, the 950PR relies on its high FP8/FP4 FLOPS rather than ultra-high memory bandwidth. - Ascend 950DT (Decode & Training): Upgraded to HiZQ 2.0 HBM (144 GB capacity at 4.0 TB/s).
The token decode phase and multi-node model pre-training are heavily memory-bound; matching the H20's 4.0 TB/s memory bandwidth allows the 950DT to process large KV-cache buffers without token latency stalls.
Memory Bandwidth Comparison (TB/s)
Ascend 950PR (HiBL) [== 1.6 TB/s ]
Nvidia H20 (HBM3) [====================== 4.0 TB/s ======================]
Ascend 950DT (HiZQ) [====================== 4.0 TB/s ======================]
Real-World Inference Performance Realities
1. Small Batch Sizes & Single-User Latency (Bandwidth-Bound)
- At Batch Size = 1 (or small context windows), LLM inference throughput depends almost entirely on memory bandwidth (fetching weights per token generated).
- Nvidia H20 and Ascend 950DT perform comparably in small-batch token generation because both chips feature a 4.0 TB/s memory bus.
- Ascend 950PR lags behind in single-user decode speed due to its 1.6 TB/s memory bandwidth, making it less suitable for real-time streaming decode tasks.
2. Large Batch Sizes, Long-Context, & Prefill (Compute-Bound)
- At Batch Size $\ge$ 32 or during massive prompt processing (100k+ token context prefill), inference transitions from memory-bound to compute-bound.
- Here, both Ascend 950PR and 950DT significantly outperform the Nvidia H20. Driven by ~1,000 FP8 TFLOPS and native FP4 support, the 950 series achieves up to 2.8x to 3.0x higher total inference throughput in high-concurrency enterprise deployments.
Trade-Offs & Strategic Takeaways
- Power Consumption & Thermal Density: Achieving high compute performance on SMIC's 7nm process requires significantly higher power. The Ascend 950PR/DT modules consume 600W to 900W+, compared to the Nvidia H20's 400W thermal footprint.
This necessitates direct-to-chip liquid cooling infrastructure in data centers scaling large 950-series clusters. - Software Integration (CUDA vs TileLang/CANN): While the Nvidia H20 benefits from plug-and-play CUDA, PyTorch, and vLLM compatibility, the Ascend 950 requires custom compiler pipelines.
DeepSeek's open-sourcing of TileLang directly addresses this hurdle, providing optimized torch_npuoperators (DeepGEMM, DeepEP) to extract peak FP8/FP4 execution from Ascend hardware without CUDA.
By Jugo Ikeji-Uju.
admin@ubuntusafa.com
sappertekinc@gmail.com
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