US-China AI Competition Daily Briefing

 

US-China AI Competition Daily Briefing

1. Capital Screening & Legal Framework: Final Month of Public Consultation for COINS Act Part 851

Private equity funds, venture capital firms, and multinational corporate compliance teams are entering the final month of the public comment window for the U.S. Department of the Treasury's proposed 31 C.F.R. Part 851 rules under Title VIII of the Comprehensive Outbound Investment National Security Act (COINS Act):

                       COINS Act Outbound Screening Structure
  
      COVERED US PERSONS                    COVERED TRANSACTIONS                 COVERED FOREIGN PERSONS
┌──────────────────────────────┐     ┌──────────────────────────────┐     ┌──────────────────────────────┐
│ • US Citizens & PRs          │     │ • Equity & VC Deals          │ ──► │ • Entities in China, HK,     │
│ • Domestic Entities          │ ──► │ • Joint Ventures / Greenfield│     │   Macau, Russia, Iran,       │
│ • Controlled Foreign Subsid. │     │ • Debt w/ Equity Conversion  │     │   North Korea, Cuba, & Ven.  │
└──────────────────────────────┘     └──────────────────────────────┘     └──────────────────────────────┘

• Systematic Shift to "Superintelligence" Prohibitions: The proposed Part 851 framework systematically replaces standard references to "AI systems" with "Superintelligence (SI) systems". The rule eliminates simple post-hoc notification safety valves for foreign AI investments, moving virtually all covered equity allocations, joint ventures, and greenfield developments involving Chinese AI developers—including application-layer agent builders—directly into the prohibited tier.
  
  
• High-Performance Computing (HPC) & Supercomputing Benchmarks: The proposed rule explicitly prohibits U.S. capital commitments to foreign supercomputing systems capable of providing $\ge 100\text{ double-precision (64-bit) PFLOPS}$ or $\ge 200\text{ single-precision (32-bit) PFLOPS}$ of compute within a 41,600 cubic foot spatial envelope.
  
  
• Expanded Executive Scope: The prongs governing U.S. personnel who "knowingly direct" foreign investments—previously limited to prohibited deals—have been extended to notifiable technology transactions as well. This requires U.S. officers, directors, and investment committee members at non-U.S. entities to enforce formal, documented recusal procedures on all covered foreign deals.
  
  
• December 7 Comment Deadline: Public submissions remain open through December 7, 2026, after which Treasury will begin drafting final rules for statutory enactment by late Q1 2027. Existing Part 850 regulations remain fully active and enforceable in the interim.
  
  

2. Export Controls & Policy: 7 Days to MOFCOM Announcement No. 48 Consultation Close

Cross-border legal and trade compliance teams are entering the final week of public consultations for China’s proposed revisions to its Catalogue of Technologies Prohibited or Restricted from Export (MOFCOM/MOST Announcement No. 48), which close on November 15, 2026:

                     China MOFCOM Pre-Export Registration Gate
  
       DRAFT CONSULTATION PERIOD               PRE-EXPORT REGISTRATION            COMMERCIAL API EXEMPTION
 ┌───────────────────────────────────┐     ┌───────────────────────────────────┐     ┌───────────────────────────────────┐
 │ • Revisions open for public       │ ──► │ • Interim rules MANDATORY since   │ ──► │ • Cloud APIs, mobile apps, &      │
 │   comments through Nov 15, 2026   │     │   Oct 16, 2026 across 23 AI tech  │     │   SaaS endpoints remain EXEMPT    │
 └───────────────────────────────────┘     └───────────────────────────────────┘     └───────────────────────────────────┘

• Scope of the 40 Proposed Controls: The draft catalog adds 40 technologies across artificial intelligence (23 items), photovoltaics (12 items), and biomedicine (5 items). Of these, 14 are Prohibited (banned outright) and 26 are Restricted (requiring state licensing).
  
  
• Granular AI Triggers: A foundation model falls under the Restricted Tier if it hits any one of three thresholds: cumulative pre-training compute $\ge 10^{26}\text{ FLOPs}$, parameter count $\ge 2\text{ Trillion}$, or a Global Top-10 Position on public benchmark rankings or call volume at the time of export. The draft also restricts autonomous AI agent frameworks ($\ge 60$ concurrent agents or $\ge 20$ subtask planning chains) and 10,000-card cluster scheduling IP.
  
  
• Mandatory Pre-Export Registration Enforced: While public consultation continues through mid-November, a mandatory temporary pre-export registration obligation has been active since October 16 for all covered transactions initiated after that date.
  
  
• The Commercial API Exemption: Official MOFCOM guidance reaffirms the boundary: providing global access to models deployed in China via cloud APIs, web portals, mobile apps, or SaaS platforms does not constitute a technology export, allowing Chinese AI firms to commercialize services globally as long as underlying weights remain anchored within domestic data centers.
  
  

3. Hardware Scaling & Infrastructure: DeepSeek's 160K Ascend Pre-Training Pivot

Technical details surrounding DeepSeek’s pre-training pipeline reveal an ambitious hardware shift to sovereign domestic silicon ahead of Huawei's scheduled Ascend cluster debut:

              Single-Chip Output vs. Massive Spatial Scale
  
      NVIDIA GB300 ACCELERATOR POD                   HUAWEI ASCEND 950DT MEGACLUSTER
 ┌──────────────────────────────────┐      ┌────────────────────────────────────────┐
 │ • ~40,000 Chips (Base Target)   │      │ • ~160,000 Chips (Ulanqab Pod)         │
 │ • Native High FP8/FP4 FLOPS     │  VS  │ • Compute Efficiency Penalty (~4:1)    │
 │ • High NVLink Fabric Throughput │      │ • Compensated by Spatial Footprint     │
 └──────────────────────────────────┘      └────────────────────────────────────────┘

• Pivot from Inference to Pre-Training: DeepSeek has officially redirected its planned 160,000-chip fleet at the Ulanqab data center in Inner Mongolia from serving inference requests to conducting full pre-training for DeepSeek V5. While a 4-to-1 ratio of Ascend 950DT chips to Nvidia GB300 GPUs is required to match compute throughput, the lab is absorbing the higher power and physical footprint to secure supply chain independence.
  
  
• On-Site Huawei Engineering Teams: To overcome historical stability issues during multi-month training runs, Huawei engineers are embedded inside DeepSeek’s Hangzhou headquarters. The teams are co-designing the microarchitecture of upcoming Ascend 960DT silicon (slated for Q1 2027) around DeepSeek’s real-world memory and low-precision math bottlenecks.
  
  
• High-Utilization Software Abstractions via TileLang: Using the co-developed, open-source TileLang compiler layer, DeepSeek engineers compile custom operators (DeepGEMM, DeepEP) directly to Ascend matrix engines, extracting near-peak execution from domestic silicon while bypassing Nvidia CUDA dependencies.
  
  

Strategic Takeaway

The US-China AI dynamic continues to operate under a bipolar structural equilibrium. Washington is formalizing administrative capital screening (via Treasury's proposed Part 851 COINS Act rules) and anti-distillation policy to protect Western capital and proprietary software models, while Beijing is deploying pre-export registration controls and sovereign hardware co-design (DeepSeek, Huawei, TileLang) to establish a CUDA-independent global computing ecosystem.

The decision by Hangzhou-based AI lab DeepSeek to pre-train its next-generation foundation model, DeepSeek V5, on a 160,000-card cluster of Huawei Ascend 950DT processors in Ulanqab, Inner Mongolia marks a fundamental operational pivot.

While domestic Chinese AI labs previously reserved Huawei NPUs for downstream inference while running compute-intensive pre-training on clusters of Nvidia GPUs, DeepSeek and Huawei have co-engineered a CUDA-independent hardware-software stack capable of frontier-scale pre-training.

1. Spatial Compute Scaling & Microarchitectural Trade-Offs

To overcome single-chip microarchitectural efficiency limits relative to Western hardware (such as Nvidia’s Blackwell SM100 platform), DeepSeek relies on massive spatial scaling across a 1-Gigawatt facility footprint in Ulanqab.

               Single-Chip Throughput vs. Massive Spatial Scale
  
      NVIDIA GB300 ACCELERATOR POD                   HUAWEI ASCEND 950DT MEGACLUSTER
 ┌──────────────────────────────────┐      ┌────────────────────────────────────────┐
 │ • ~40,000 Chips (Base Target)   │      │ • ~160,000 Chips (Ulanqab Pod)  │
 │ • Native High FP8/FP4 FLOPS     │  VS  │ • Compute Efficiency Penalty (~4:1)    │
 │ • High NVLink Fabric Throughput │      │ • Compensated by Spatial Footprint     │
 └──────────────────────────────────┘      └────────────────────────────────────────┘

• Spatial Scale Compensation: Internal benchmark evaluations indicate that roughly four Huawei Ascend 950DT NPU accelerators are required to match the raw FP8/FP4 matrix throughput of a single Nvidia GB300 accelerator under full pre-training workloads. Rather than scaling back model parameters, DeepSeek absorbs a 4:1 hardware efficiency penalty by expanding the physical cluster size to 160,000 active nodes.
  
  
• High-Bandwidth Memory (HBM) Sourcing: The Ascend 950DT utilizes domestic 3D-stacked HiBL/HiZQ memory architectures. Although per-chip memory bus bandwidth remains constrained compared to Western HBM3e/HBM4 offerings, the 160,000-card aggregate memory pool allows DeepSeek V5 to maintain massive model parameter states in local high-speed memory without frequent offloading to host system RAM.
  
  
• Power Budgeting in Ulanqab: Operating 160,000 NPU accelerators along with server nodes, cooling systems, and networking hardware requires over 1 Gigawatt of continuous power. Deploying the megacluster in Ulanqab, Inner Mongolia provides direct access to cheap, subsidized wind and solar power grids, while low ambient air temperatures enable free-air heat exchange to reduce free-cooling PUE.
  
  

2. Software Acceleration Layer: Bypassing CUDA via TileLang & CANN 9.20

Executing a multi-trillion parameter training run across 160,000 non-Nvidia NPUs requires a custom software abstraction layer to prevent driver instability, communication drops, and thread starvation.

              Ascend NPU Software Abstraction Stack
  
    DEEPSEEK V5 MODEL PARADIGM (Sparse Mixture-of-Experts)
 ┌────────────────────────────────────────────────────────┐
 │  TileLang Domain-Specific Language (Hardware Agnostic)│
 ├────────────────────────────────────────────────────────┤
 │  Custom Ascend Kernels: DeepGEMM | DeepEP | FlashMLA  │
 ├────────────────────────────────────────────────────────┤
 │  Huawei CANN 9.20 Driver Runtime & Task Scheduler      │
 ├────────────────────────────────────────────────────────┤
 │  160,000-Card Ascend 950DT Physical Hardware Cluster  │
 └────────────────────────────────────────────────────────┘

• TileLang Compilation Engine: Co-developed by DeepSeek and Huawei, TileLang serves as an open-source, hardware-neutral domain-specific programming language. By compiling custom kernel operators directly into low-level machine code for Huawei's Vector and Cube execution engines, TileLang extracts up to 95%+ of peak hardware FLOPS on Ascend NPUs while bypassing Nvidia's proprietary CUDA runtime layer.
  
  
• DeepGEMM & DeepEP Ascend Ports: DeepSeek open-sourced native Ascend versions of its core acceleration libraries:
  
  
  • DeepGEMM (FP8 Matrix Multiplication): Optimized for low-precision tensor core operations, allowing fine-grained FP8/FP4 mixed-precision matrix multiplication directly on Ascend Cube cores.
    
    
  • DeepEP (MoE Expert Parallelism): Handles token-routing communication across Mixture-of-Experts (MoE) layers, reducing inter-node token transfer latencies across massive NPU groups.
    
    
• CANN 9.20 Runtime Hardening: Huawei's Compute Architecture for Neural Networks (CANN 9.20) toolkit handles low-level task queue scheduling and hardware abstraction. Embedded DeepSeek and Huawei engineers deployed custom fault-tolerance routines within CANN to automatically bypass failed NPU nodes or corrupted memory banks in real time, preventing multi-day cluster crashes during large-scale pre-training runs.
  
  

3. Cluster Topology & Scale-Out Fabric

The primary obstacle when scaling an AI cluster to 160,000 nodes is all-to-all communication latency during gradient synchronization and MoE token dispatch.

                160,000-Card Cluster Topology & Interconnect
  
     INTRA-POD INTERCONNECT                    INTER-CLUSTER SCALE-OUT FABRIC
 ┌──────────────────────────────┐          ┌───────────────────────────────────┐
 │ • 128-Card SuperPod Modules  │─► │ • Lingqu UnifiedBus Interconnect  │
 │ • High-Bandwidth Direct Mesh │          │ • Optical Circuit Switches (OCS)  │
 │ • Low-Latency MoE Routing    │          │ • Automated Topology Re-routing   │
 └──────────────────────────────┘          └───────────────────────────────────┘

• 128-Card SuperPod Architecture: The Ulanqab cluster is constructed using Huawei-designed 128-card SuperPod modules. Within each 128-card module, NPUs communicate via direct PCB and backplane interconnects, allowing rapid intra-pod tensor and pipeline parallelism without passing traffic through external network switches.
  
  
• Lingqu UnifiedBus Interconnect: To link over 1,200 SuperPod units into a unified 160,000-card mesh, Huawei deployed its proprietary Lingqu UnifiedBus interconnect alongside custom optical circuit switches (OCS). This scale-out fabric delivers non-blocking bandwidth across cluster segments, preventing network bottlenecks during MoE token routing.
  
  

Strategic Engineering Significance

DeepSeek’s pre-training strategy for V5 demonstrates that hardware throughput gaps can be offset through software compiler co-design (TileLang), efficient architectural algorithms (Sparse MoE + FP8/FP4), and massive spatial cluster scaling.

By executing a 160,000-card Ascend 950DT cluster in Inner Mongolia, DeepSeek and Huawei are proving the viability of a sovereign, CUDA-independent computing ecosystem capable of sustaining frontier-scale AI development despite strict U.S. semiconductor export controls.

By Jugo Ikeji Uju

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