US-China AI Competition Daily Briefing

 

US-China AI Competition Daily Briefing

1. Capital Screening & Legal Enforcement: COINS Act NPRM Deepens Scrutiny on Derivative Agents

As the December 7, 2026 public comment deadline approaches for the U.S. Department of the Treasury's proposed 31 C.F.R. Part 851 rules implementing Title VIII of the Comprehensive Outbound Investment National Security Act (COINS Act), legal compliance teams are highlighting an expanded enforcement risk:

• The "Derivative Development" Trigger: Legal analyses emphasize that Part 851 systematically replaces "AI systems" with "Superintelligence (SI) systems" and expands the legal definition of "development". A foreign entity is classified as developing an SI system if it builds agentic harnesses, orchestration wrappers, or fine-tuned extensions on top of third-party frontier models—even if it did not pre-train the underlying base weights.
  
  
• Elimination of Notification Carve-Outs: The proposed rule eliminates the prior two-tiered split (prohibited vs. notifiable) for AI deals. All covered U.S. venture allocations, private equity investments, joint ventures, and greenfield developments involving Chinese AI developers—including application-layer agent builders—are pushed directly into the prohibited tier.
  
  
• Executive Recusal Mandates: The "knowingly directing" prohibition extends executive liability to notifiable technology transactions (in semiconductors, HPC, and biotech). U.S. officers and directors serving on offshore funds must enforce formal, documented recusal procedures on all covered foreign deals.
  
  

2. Export Controls & Policy: 8 Days to MOFCOM Announcement No. 48 Consultation Close

Cross-border corporate compliance teams are entering the final week of public consultations for China’s proposed revisions to its Catalogue of Technologies Prohibited or Restricted from Export (MOFCOM/MOST Announcement No. 48), which close on November 15, 2026:

                     China MOFCOM Pre-Export Registration Gate
  
       DRAFT CONSULTATION PERIOD               PRE-EXPORT REGISTRATION            COMMERCIAL API EXEMPTION
 ┌───────────────────────────────────┐     ┌───────────────────────────────────┐     ┌───────────────────────────────────┐
 │ • Revisions open for public       │ ──► │ • Interim rules MANDATORY since   │ ──► │ • Cloud APIs, mobile apps, &      │
 │   comments through Nov 15, 2026   │     │   Oct 16, 2026 across 23 AI tech  │     │   SaaS endpoints remain EXEMPT    │
 └───────────────────────────────────┘     └───────────────────────────────────┘     └───────────────────────────────────┘

• Mandatory Interim Registration Enforced: Although final rules are pending post-consultation, a mandatory temporary pre-export registration requirement has been enforced since October 16. Domestic Chinese AI labs and cross-border joint ventures must declare recipient details, end-uses, and technical specs for covered weight transfers ($\ge 2\text{ Trillion}$ parameters or $\ge 10^{26}\text{ FLOPs}$ compute), autonomous agent swarms ($\ge 60$ agents), and 10,000-card cluster scheduling IP before completing foreign transfers.
  
  
• The Commercial API Line: Official Ministry of Commerce guidance reaffirms the boundary: providing global AI model access via cloud APIs, web portals, mobile apps, and SaaS platforms does not constitute a technology export, preserving cloud revenue streams for Chinese AI providers as long as physical weights remain on domestic servers.
  
  

3. Hardware Scaling & Infrastructure: DeepSeek's 160,00 Ascend Pre-Training Pivot

Technical details surrounding DeepSeek’s pre-training pipeline reveal an ambitious hardware shift to sovereign domestic silicon ahead of Huawei's scheduled Ascend cluster debut:

• Pivot from Inference to Pre-Training: DeepSeek has officially redirected its planned 160,000-chip fleet at the Ulanqab data center in Inner Mongolia from serving inference requests to conducting full pre-training for DeepSeek V5. Founder Liang Wenfeng noted that while a 4-to-1 ratio of Ascend 950DT chips to Nvidia GB300 GPUs is required to match compute throughput, the lab is absorbing the higher power and physical footprint to secure supply chain independence.
  
  
• On-Site Huawei Engineering Teams: To overcome historical stability issues during multi-month training runs, Huawei engineers are embedded inside DeepSeek’s Hangzhou headquarters. The teams are co-designing the microarchitecture of upcoming Ascend 960DT silicon (slated for Q1 2027) around DeepSeek’s real-world memory and low-precision math bottlenecks.
  
  
• High-Utilization Software Abstractions: Using custom open-source libraries, DeepSeek reports achieving over 95% of peak Ascend 950 performance in internal pre-training tests. By releasing these Ascend-optimized libraries publicly, DeepSeek is building a CUDA-independent software ecosystem for domestic developers.
  
  

Strategic Takeaway

The US-China AI competition has reached an operational turning point. While U.S. outbound capital screening (via Treasury's proposed Part 851 rules) expands to capture application-layer software and agent wrappers, sovereign Chinese labs (DeepSeek, Huawei) are absorbing a 4:1 hardware efficiency penalty to transition multi-hundred-thousand-card pre-training clusters entirely onto domestic silicon.

The decision by Hangzhou-based AI lab DeepSeek to transition its upcoming flagship model, DeepSeek V5, onto a 160,000-card cluster of Huawei Ascend 950DT accelerators at a greenfield megacluster site in Ulanqab, Inner Mongolia represents a pivotal moment in sovereign AI hardware scaling.

Historically, domestic Chinese labs reserved Huawei NPU clusters for downstream inference while running compute-intensive pre-training on clusters of Nvidia GPUs. The technical architectural breakdown below illustrates how DeepSeek and Huawei are overcoming compute throughput penalties, memory bandwidth limits, and cluster interconnect bottlenecks to execute frontier-scale pre-training completely independent of Western hardware or Nvidia's CUDA runtime.

1. Hardware Architecture & Silicon Compute Trade-Offs

To compensate for single-chip microarchitecture performance gaps relative to Western hardware (such as Nvidia’s Blackwell SM100 architecture), DeepSeek relies on massive spatial scaling.

               Single-Chip Output vs. Massive Spatial Scale
  
      NVIDIA GB300 ACCELERATOR POD                   HUAWEI ASCEND 950DT MEGACLUSTER
 ┌──────────────────────────────────┐      ┌────────────────────────────────────────┐
 │ • ~40,000 Chips (Base Target)   │      │ • ~160,000 Chips (Ulanqab Pod)         │
 │ • Native High FP8/FP4 FLOPS     │  VS  │ • Compute Efficiency Penalty (~4:1)    │
 │ • High NVLink Fabric Throughput │      │ • Compensated by Spatial Footprint     │
 └──────────────────────────────────┘      └────────────────────────────────────────┘

• Compute Density & Throughput Scaling: Internal benchmark estimates indicate that approximately four Huawei Ascend 950DT NPU accelerators are required to match the raw FP8/FP4 matrix throughput of a single Nvidia GB300 GPU under full training workloads. Rather than reducing model complexity, DeepSeek absorbs a 4:1 hardware efficiency penalty by expanding cluster size to 160,000 active nodes.
  
  
• High-Bandwidth Memory (HBM) Sourcing: The Ascend 950DT leverages domestic 3D-stacked HiBL/HiZQ memory architectures. While per-chip memory bandwidth remains constrained compared to Western HBM3e/HBM4 offerings, the 160,000-card aggregate memory pool allows DeepSeek V5 to maintain massive model parameter states in high-speed local memory without frequent offloading to main system RAM.
  
  
• Power & Thermal Budgeting in Inner Mongolia: Operating 160,000 NPU accelerators along with server nodes, cooling systems, and networking hardware demands a continuous power load of over 1.2 Gigawatts. Deploying the cluster in Ulanqab, Inner Mongolia provides direct access to cheap, subsidized wind and solar power grids, while low ambient air temperatures reduce cooling overhead through free-air heat exchange.
  
  

2. Software Acceleration Layer: Bypassing CUDA via TileLang & CANN 9.20

Executing a multi-trillion parameter training run across 160,000 non-Nvidia NPUs requires a custom software abstraction layer to prevent driver instability, communication drops, and thread starvation.

              Ascend NPU Software Abstraction Stack
  
    DEEPSEEK V5 MODEL PARADIGM (Sparse Mixture-of-Experts)
 ┌────────────────────────────────────────────────────────┐
 │  TileLang Domain-Specific Language (Hardware Agnostic) │
 ├────────────────────────────────────────────────────────┤
 │  Custom Ascend Kernels: DeepGEMM | DeepEP | FlashMLA   │
 ├────────────────────────────────────────────────────────┤
 │  Huawei CANN 9.20 Driver Runtime & Task Scheduler     │
 ├────────────────────────────────────────────────────────┤
 │  160,000-Card Ascend 950DT Physical Hardware Cluster   │
 └────────────────────────────────────────────────────────┘

• TileLang Compilation Engine: Co-developed by DeepSeek and Huawei, TileLang serves as an open-source, hardware-neutral domain-specific programming layer. By compiling custom kernel operators directly into low-level machine code for Huawei's Vector/Cube execution engines, TileLang extracts up to 95%+ of peak hardware FLOPS on Ascend NPUs while bypassing Nvidia's proprietary CUDA runtime layer.
  
  
• DeepGEMM & DeepEP Porting: DeepSeek released native Ascend ports for its core kernel acceleration libraries:
  
  
  • DeepGEMM (FP8 Matrix Multiplication): Optimized for low-precision tensor core operations, allowing fine-grained FP8/FP4 mixed-precision matrix multiplication directly on Ascend Cube cores.
    
    
  • DeepEP (MoE Expert Parallelism): Handles token-routing communication across Mixture-of-Experts (MoE) layers, reducing inter-node token transfer latencies across massive NPU groups.
    
    
• CANN 9.20 Runtime Hardening: Huawei's Compute Architecture for Neural Networks (CANN 9.20) toolkit handles low-level task queue scheduling and hardware abstraction. DeepSeek and Huawei engineers deployed custom fault-tolerance routines within CANN to automatically bypass failed NPU nodes or corrupted memory banks in real time, preventing multi-day cluster crashes during large-scale pre-training runs.
  
  

3. Cluster Interconnect & Inter-Node Communication

The main bottleneck when scaling an AI cluster to 160,000 nodes is all-to-all communication latency during gradient synchronization and MoE token routing.

                160,000-Card Cluster Topology & Interconnect
  
     INTRA-POD INTERCONNECT                    INTER-CLUSTER SCALE-OUT FABRIC
 ┌──────────────────────────────┐          ┌───────────────────────────────────┐
 │ • 128-Card SuperPod Pods    │  ──────► │ • Lingqu UnifiedBus Interconnect  │
 │ • High-Bandwidth Direct Mesh │          │ • Optical Circuit Switches (OCS)  │
 │ • Ultra-Low Latency MoE Mesh │          │ • Automated Topology Re-routing   │
 └──────────────────────────────┘          └───────────────────────────────────┘

• 128-Card SuperPod Architecture: The Ulanqab cluster is built using 128-card SuperPod modules. Within each 128-card module, NPUs communicate via direct, high-bandwidth PCB and backplane interconnects, allowing rapid intra-pod tensor and pipeline parallelism without going through external switches.
  
  
• Lingqu UnifiedBus & Scale-Out Fabric: To link over 1,200 SuperPod units into a unified 160,000-card mesh, Huawei deployed its proprietary Lingqu UnifiedBus interconnect and custom optical circuit switches (OCS). This topology provides non-blocking, multi-terabit bandwidth across cluster segments, mitigating network congestion when routing tokens across distributed MoE expert layers.
  
  

Strategic Engineering Significance

DeepSeek’s pre-training strategy for V5 demonstrates that hardware performance penalties can be mitigated through custom software compiler co-design (TileLang), efficient architectural algorithms (Sparse MoE + FP8/FP4), and massive spatial cluster scaling.

By successfully running a 160,000-card Ascend cluster in Inner Mongolia, DeepSeek and Huawei are establishing a robust, sovereign, and CUDA-independent computing stack capable of sustaining frontier AI model development despite strict Western semiconductor export controls.

By Jugo Ikeji Uju

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